Characterization of Charge-Trap-Transistor (CTT) Threshold Voltage Degradation and Differential-Pair-Based Memory Design
Published in 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023
This work characterizes threshold-voltage degradation in programmed charge-trap transistors and proposes a differential-pair-based memory architecture that mitigates degradation for long-term analog value storage.
Recommended citation: Zhichao Chen, Yang Xiao, Li Du, and Yuan Du. (2023). "Characterization of Charge-Trap-Transistor (CTT) Threshold Voltage Degradation and Differential-Pair-Based Memory Design." 2023 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5.
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